Some embodiments of the invention described below are related to methodologies for testing manufactured computer systems, and in particular their main memory subsystems, to determine whether electrical specifications for chip-to-chip connections (also referred to here as interconnects) have been met, as well as whether the integrated circuit (IC) devices in the main memory subsystem have been assembled or installed correctly. Other embodiments are also described and claimed.
Industry trends for high performance computer systems, such as those that use a Pentium processor and associated system chipset by Intel Corp., Santa Clara, California, are towards faster product cycle times (time to market) with sustained high quality. At the same time, chip-to-chip connection or bus speeds are increasing to several hundred megahertz and, in the case of serial links, beyond several gigahertz (GHz). Device pin densities are also increasing, again to meet the need for greater performance in the computer system. These demands render conventional testing techniques such as oscilloscope and logic analyzer probing less reliable, and often impossible particularly on high speed interfaces, both in the high volume manufacturing setting, as well as earlier in the electrical validation and verification stage of device and platform manufacturing.
At the board and platform level, the system has its primary components, including the processor, system chipset, and memory, installed on a motherboard. In that stage of manufacturing, transaction-based tests have been used, in a board or platform high volume manufacturing setting, to verify a wide range of storage and logic functions of the system. Such tests evaluate whether the memory subsystem and the I/O subsystem work according to their electrical specifications. The test is performed by the processor executing a special test routine, during or after booting an operating system (OS) program, that causes test patterns that are part of the test routine to be written to and then read from addresses that span the computer system. However, faults of a high frequency type (such as due to cross talk between adjacent signal lines and inter-symbol interference (ISI) due to transmission line effects) cannot be detected or isolated using such techniques, due to the coarse test granularity and high instruction overhead associated with running an OS-based test program.
Another type of computer system test calls for the processor to execute firmware/software that operates at a lower level than an OS-based program, prior to booting the operating system. These include basic I/O system (BIOS) and extended firmware interface (EFI) programs. Although these types of tests provide relatively low-level, and hence more accurate, control of component functionality and interconnect buses, system interactions cannot be stressed to their bandwidth specifications in such tests. In addition, the ability of BIOS/EFI tests to isolate a fault with sufficient granularity is also limited.
Finally, there is a low level technique known as boundary scan testing (or the Joint Test Access Group, JTAG, protocol) which calls for on-chip circuitry used to control individual bits transmitted between components. Once again, however, there is no provision for testing high frequency faults. For example, a boundary scan test may detect “opens” and “shorts” while running at a 10 MHz clock, whereas normal signaling speed on the interconnect will be in the hundreds of MHz or even GHz range.